In semiconductor storage devices such as a NAND flash memory, memory cells are increasingly downscaled. As the downscaling of memory cells progresses, gaps between adjacent charge accumulation layers become narrower, and it becomes difficult to embed a control gate between the charge accumulation layers. To deal with this problem, it is necessary to make the physical thickness of an IPD (Inter-Poly Dielectric) film between a charge accumulation layer and a control gate thinner.
However, when the IPD film is made thinner, the charge amount de-trapped from the IPD film increases. That is, when the IPD film is made thinner, charges once trapped in the IPD film tend to be easily released to a charge accumulation layer or a control gate. For example, when a positive voltage is applied on a control gate, electrons trapped in the IPD film are pushed out to the control gate. Changes of the charge amount within the IPD film affect the threshold voltage of memory cells. Therefore, if charges are trapped in the IPD film, it is not preferable that the charges are de-trapped from the IPD film. It is needless to mention that if the charge amount trapped in the IPD film is decreased, the charge amount de-trapped from the IPD film is also decreased.
Meanwhile, charges to be trapped in the IPD film relax an electric field caused in the IPD film at the time of data writing and reduce a leakage current. Accordingly, the charges prevent electrons from leaking from a floating gate and maintain write saturation.
Therefore, it has been desired that leakage of electrons is suppressed while decreasing charges trapped in an IPD film and/or charges de-trapped from the IPD film even if the IPD film is made thinner.